Nonlinear Analysis of the 2 nd Order Digital Phase Locked loop
نویسندگان
چکیده
_______________________________________________________________________________ Abstract— This paper proposes a rigorous stability criterion for the 2 order digital phase locked loop (DPLL), with a charge pump phase frequency detector (CP-PFD) component. The Stability boundary is determined using piecewise linear methods to model the non-linear nature of the CP-PFD component block. It calculates the control voltage, after a predetermined number of input reference signal sampling periods, to a small initial voltage offset. Using this piecewise linear model an exact closed form stability criterion is proposed for the second order system. The 2 order stability boundaries, as defined by the proposed technique, are compared to that of existing linear theory stability boundaries, and display a significant improvement.
منابع مشابه
Closed-Form Analytical Equations to Transient Analysis of Bang-Bang Phase-Locked Loops
Due to the nonlinear nature of the Bang-Bang phase-locked loops (BBPLLs), its transient analysis is very difficult. In this paper, new equations are proposed for expression of transient behavior of the second order BBPLLs to phase step input. This approach gives new insights into the transient behavior of BBPLLs. Approximating transient response to reasonable specific waveform the loop tran...
متن کاملLow Settling Time All Digital DLL For VHF Application
Settling time is one of the most important parameter in design of DLLs. In this paper we propose a new high speed with low settling time Delay Locked Loop (DLL) in which a digital signal processor (DSP) is used instead of using phase-frequency detector, charge pump and loop filter in conventional DLL. To have better settling time, PRP conjugate gradient algorithm is used to optimize delay of ea...
متن کاملHigh Speed Delay-Locked Loop for Multiple Clock Phase Generation
In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...
متن کاملDesign and Implementation of Digital Demodulator for Frequency Modulated CW Radar (RESEARCH NOTE)
Radar Signal Processing has been an interesting area of research for realization of programmable digital signal processor using VLSI design techniques. Digital Signal Processing (DSP) algorithms have been an integral design methodology for implementation of high speed application specific real-time systems especially for high resolution radar. CORDIC algorithm, in recent times, is turned out to...
متن کاملDual Phase Detector Based Delay Locked Loop for High Speed Applications
In this paper a new architecture for delay locked loops will be presented. One of problems in phase-frequency detectors (PFD) is static phase offset or reset path delay. The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and outpu...
متن کامل